GhostMinion: A Strictness-Ordered Cache System for Spectre Mitigation

Out-of-order speculation, a technique ubiquitous since the early 1990s, remains a fundamental security flaw. Via attacks such as Spectre and Meltdown, an attacker can trick a victim, in an otherwise entirely correct program, into leaking its secrets through the effects of misspeculated execution, in a way that is entirely invisible to the programmer's model. This has serious implications for application sandboxing and inter-process communication. Designing efficient mitigations, that preserve the performance of out-of-order execution, has been a challenge. The speculation-hiding techniques in the literature have been shown to not close such channels comprehensively, allowing adversaries to redesign attacks. Strong, precise guarantees are necessary, but at the same time mitigations must achieve high performance to be adopted. We present Strictness Ordering, a new constraint system that shows how we can comprehensively eliminate transient side channel attacks, while still allowing complex speculation and data forwarding between speculative instructions. We then present GhostMinion, a cache modification built using a variety of new techniques designed to provide Strictness Order at only 2.5% overhead

Software Prefetching for Indirect Memory Accesses

Many modern data processing and HPC workloads are heavily memory-latency bound. A tempting proposition to solve this is software prefetching, where special non-blocking loads are used to bring data into the cache hierarchy just before being required. However, these are difficult to insert to effectively improve performance, and techniques for automatic insertion are currently limited. This paper develops a novel compiler pass to automatically generate software prefetches for indirect memory accesses, a special class of irregular memory accesses often seen in high-performance workloads. We evaluate this across a wide set of systems, all of which gain benefit from the technique. We then evaluate the extent to which good prefetch instructions are architecture dependent. Across a set of memory-bound benchmarks, our automated pass achieves average speedups of 1.3$\times$ and 1.1$\times$ for an Intel Haswell processor and an ARM Cortex-A57, both out-of-order cores, and performance improvements of 2.1$\times$ and 3.7$\times$ for the in-order ARM Cortex-A53 and Intel Xeon Phi

Vector Runahead for Indirect Memory Accesses

Vector runahead delivers extremely high memory-level parallelism even for the chains of dependent memory accesses with complex intermediate address computation, which conventional runahead techniques fundamentally cannot handle and, therefore, have ignored. It does this by rearchitecting runahead to use speculative data-level parallelism, rather than work skipping, as its primary form of extracting more memory-level parallelism in runahead mode than a true execution can, which we hope will bring about an entirely new dimension for high-performance processors

ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance.

Providing reliability is becoming a challenge for chip manufacturers, faced with simultaneously trying to improve miniaturization, performance and energy efficiency. This leads to very large margins on voltage and frequency, designed to avoid errors even in the worst case, along with significant hardware expenditure on eliminating voltage spikes and other forms of transient error, causing considerable inefficiency in power consumption and performance. We flip traditional ideas about reliability and performance around, by exploring the use of error resilience for power and performance gains. ParaMedic is a recent architecture that provides a solution for reliability with low overheads via automatic hardware error recovery. It works by splitting up checking onto many small cores in a heterogeneous multicore system with hardware logging support. However, its design is based on the idea that errors are exceptional. We transform ParaMedic into ParaDox, which shows high performance in both error-intensive and scarce-error scenarios, thus allowing correct execution even when undervolted and overclocked. Evaluation within error-intensive simulation environments confirms the error resilience of ParaDox and the low associated recovery cost. We estimate that compared to a non-resilient system with margins, ParaDox can reduce energy-delay product by 15% through undervolting, while completely recovering from any induced errors

Implementing Time Travel for the Web

This article discusses the challenges and solutions discovered for implementing the Memento protocol in a variety of browser environments. It describes the design and deployment of the client technologies which have been developed: a web application that functioned as a browser, an add-on for FireFox called MementoFox, a plugin for Internet Explorer and an Android-based client application. The design and technical solutions identified during the development will be of interest to those considering implementation of a Memento based platform, especially on the client side, however the interactions are also important for building conformant server-side systems

Rewriting History: Repurposing Domain-Specific CGRAs

Coarse-grained reconfigurable arrays (CGRAs) are domain-specific devices promising both the flexibility of FPGAs and the performance of ASICs. However, with restricted domains comes a danger: designing chips that cannot accelerate enough current and future software to justify the hardware cost. We introduce FlexC, the first flexible CGRA compiler, which allows CGRAs to be adapted to operations they do not natively support. FlexC uses dataflow rewriting, replacing unsupported regions of code with equivalent operations that are supported by the CGRA. We use equality saturation, a technique enabling efficient exploration of a large space of rewrite rules, to effectively search through the program-space for supported programs. We applied FlexC to over 2,000 loop kernels, compiling to four different research CGRAs and 300 generated CGRAs and demonstrate a 2.2$\times$ increase in the number of loop kernels accelerated leading to 3$\times$ speedup compared to an Arm A5 CPU on kernels that would otherwise be unsupported by the accelerator

Feasibility study for supporting medication adherence for adults with cystic fibrosis: mixed-methods process evaluation

Objectives: To undertake a process evaluation of an adherence support intervention for people with cystic fibrosis (PWCF), to assess its feasibility and acceptability. Setting: Two UK cystic fibrosis (CF) units. Participants: Fourteen adult PWCF; three professionals delivering adherence support (‘interventionists’); five multi-disciplinary CF team members. Interventions: Nebuliser with data recording and transfer capability, linked to a software platform, and strategies to support adherence to nebulised treatments facilitated by interventionists over 5 months (± 1 month). Primary and secondary measures: Feasibility and acceptability of the intervention, assessed through semistructured interviews, questionnaires, fidelity assessments and click analytics. Results: Interventionists were complimentary about the intervention and training. Key barriers to intervention feasibility and acceptability were identified. Interventionists had difficulty finding clinic space and time in normal working hours to conduct review visits. As a result, fewer than expected intervention visits were conducted and interviews indicated this may explain low adherence in some intervention arm participants. Adherence levels appeared to be >100% for some patients, due to inaccurate prescription data, particularly in patients with complex treatment regimens. Flatlines in adherence data at the start of the study were linked to device connectivity problems. Content and delivery quality fidelity were 100% and 60%–92%, respectively, indicating that interventionists needed to focus more on intervention ‘active ingredients’ during sessions. Conclusions: The process evaluation led to 14 key changes to intervention procedures to overcome barriers to intervention success. With the identified changes, it is feasible and acceptable to support medication adherence with this intervention. Trial registration number: ISRCTN13076797; Results